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1/40 tda7500a december 2001 n full software flexibility with two 24x24 bit dsp cores n software am/fm, audio and sound- processing n hardware rds filter, demodulator & decoder n integrated codec (4adcs, 6dacs) n iic and spi control interfaces n spi dedicated to display micro n 6 channel serial audio interface (sai) n spdif receiver with sample rate converter n external memory interface (emi) n double debug interface n on-chip pll n 5v-tolerant 3v i/o interface n 12x2 multifunction general purpose i/o ports description the tda7500a is an integrated circuit implementing a fully digital, integrated and advanced solution to perform the signal processing in front of the power amplifier and behind the am/fm tuner or any other audio source. the chip integrates two 45 mips dsp cores: one for stereo decoding, noise blanking, weak signal processing and multipath detection and one for sound processing, dolby b, echo and noise cancel- ling for the telephone. tqfp100 (with slug down) ordering number: tda7500a digital am/fm signal processor block diagram x ram 1024 y ram 1024 p ram 2048 p rom 256 2 dsp1 orpheus core fm processing, am processing, traffic memorization xchg interf. p ram 5632 p rom 512 y ram 1024 int reset 4 vdd gnd 4 dsp0 orpheus core audio processing, sound processing, debug interface 4 adcvdd adcgnd debug interface adc-ref x ram 1024 including 12 gpios including12gpios tes t grp & blk sync., error correction 4 rds filter spi demod. pll clock generator 8+3 external memory interface sram 4mx8 dram 128kx4 17 noise & echo canc. dolby b spdif 2ch. interface 2ch sample rate converter sai 6ch. receiver 2 sai transmitter 2 3 4 4 10 word spi 1 receive stack 4 spi 2 iic / spi 1 6 ch. audio bus receive bit&word clk digital audio in spdif audio in 6 channel audio bus l pcontrol display l p sd dac-ref oversampl. filter oversampl. filter oversampl. filter noise shaper noise shaper noise shaper sc filter decimation filter decimation filter clk in crystal oscillator rds error corr. rds blocks or rds clk, dat, qual rds bit/blk int. rds spi analog in sd sd sd sc filter sc filter sc filter sc filter sc filter analog audio out avdd agnd
tda7500a 2/40 description (continued) an i 2 c/spi interface is implemented for control and communication with the main micro. a separate spi is avail- able to interface the display micro.the dsp cores are integrated with their associated data and program mem- ories. the peripherals and interfaces i 2 c, spi, serial audio interface (sai), pll oscillator, external memory interface, (emi), general purpose i/o register (port a) and the d/a registers are connected to and controlled by dsp0, whereas the a/d registers, the spdif and the general purpose i/o register (port b) are connected to and controlled by dsp1. an hardware rds filter , demodulator and decoder block is also embedded. no support is needed from the dsps but at initialisation so that rds can work in background and in parallel with other dsp processing. separated debug and test interfaces are connected to both dsp cores. the tda7500a is supposed to be used in kit with the tda7501 or any other device of the same family. thanks to the serial audio interface also digital sources can be processed and a direct output to a digital bus is also available. the flexibility allowed by the wide memory space and by the two powerfull dsp cores make the tda7500a us- able for different applications. in example, inside the main radio as an audio co-processor or to perform the sig- nal processing and equalisation associated to a digital power amplifier. absolute maximum ratings warning: operation at or beyond these limit may result in permanent damage to the device. normal operation is not guaranteed at these extremes. thermal data note: 1. in still air 2. on 4 layers board with soldered slug 3. measured on top side of the package symbol parameter value unit v dd v cc power supplies digital analog -0.5 to +4.6 -0.5 to +4.6 v v v aio analog input and output voltage -0.5 to (v cc +0.5) v v dio digital input and output voltage -0.5 to (v dd +0.5) v v di5 digital input voltage (5v tolerant) -0.5 to 6.5 v t j operating junction temperature range -40 to 125 c t stg storage temperature -55 to 150 c symbol parameter value unit r th j-amb thermal resistance junction to ambient (1) 45 c/w thermal resistance junction to ambient (2) 20 c/w r th j-case thermal junction to case (3) 5 c/w
3/40 tda7500a pin description n name type description 1 gnd1 ground pin dedicated to the digital circuitry. 2 vdd1 supply pin dedicated to the digital circuitry. 3 testen i test enable (input). when low, puts the chip into test mode and muxes the xti clock to all flip-flops. when test_se is also active, the scan chain shifting is enabled. to be connected to vdd in operating mode. 4 testse i scan enable (input). when high with testen also active, controls the shifting of the internal scan chains. when active with testen not active, sets all tri-state outputs into hi-impedance mode. to be connected to gnd in operating mode. 5 nreset i system reset (input). a low level applied to nreset input initializes the ic. 6 sckm/dsp0_gpio0 i/o i 2 c serial clock line (input/output)/spi bit clock (input)/ general purpose i/o (input/output). clock line for i 2 c bus. if spi interface is enabled, behaves as spi bit clock. optionally it can be used as general purpose i/o controlled by dsp0. 7 misom/dsp0_gpio1 i/o i 2 c serial data line (input/output)/spi master input slave output serial data (input/output)/general purpose i/o (input/ output). data line for i 2 c bus. if spi is enabled, behaves as serial data input when in spi master mode and serial data output when in spi slave mode. optionally it can be used as general purpose i/o controlled by dsp0. 8 mosim/dsp0_gpio2 i/o spi master output slave input serial data (input/output)/ general purpose i/o (input/output). serial data output when in spi master mode and serial data input when in spi slave mode. optionally it can be used as general purpose i/o controlled by dsp0. 9 ssm/dsp0_gpio3 i spi slave select (input)/general purpose i/o (input/output). if spi is enabled, behaves as slave select line for spi bus. optionally it can be used as general purpose i/o controlled by dsp0. 10 sckd/dsp0_gpio4 i spi bit clock (input)/general purpose i/o (input/output). spi bit clock. optionally it can be used as general purpose i/o controlled by dsp0. 11 misod/dsp0_gpio5 i/o spi master input slave output serial data (input/output)/ general purpose i/o (input/output). behaves as serial data input when in spi master mode and serial data output when in spi slave mode. optionally it can be used as general purpose i/ o controlled by dsp0. 12 misod/dsp0_gpio6 i/o spi master output slave input serial data (input/output)/ general purpose i/o (input/output). serial data output when in spi master mode and serial data input when in spi slave mode. optionally it can be used as general purpose i/o controlled by dsp0. 13 ssd/dsp0_gpio7 i spi slave select (input)/general purpose i/o (input/output). behaves as slave select line for spi bus. optionally it can be used as general purpose i/o controlled by dsp0.
tda7500a 4/40 14 clkin i clock input pin (input). clock from external digital audio source to synchronize the internal pll. 15 avdd supply pin dedicated to the pll. 16 xti i crystal oscillator input (input). external clock input or crystal oscillator input. 17 xto o crystal oscillator output (output). crystal oscillator output drive. 18 agnd ground pin dedicated to the pll. 19 rdsint/dsp1_gpio4 o rds bit/block interrupt (output)/general purpose i/o (input/ output). provides an interrupt to the main micro. optionally it can be used as general purpose i/o controlled by dsp1. 20 rdsari_sck/dsp1_gpio3 o spi bit clock (input)/ari indicator (output)/general purpose i/o (input/output). if spi interface is enabled, behaves as spi bit clock. optionally it provides the ari indication bit. optionally it can be used as general purpose i/o controlled by dsp1. 21 rdsqal_so/dsp1_gpio2 o spi slave output serial data (output)/rds bit quality (output)/ general purpose i/o (input/output). if spi is enabled, behaves as serial data output. optionally it provides the rds serial data quality information. optionally it can be used as general purpose i/o controlled by dsp1. 22 rdsdat_si/dsp1_gpio1 i spi slave input serial data (input)/rds bit data (output)/ general purpose i/o (input/output). if spi is enabled, behaves as serial data input. optionally it provides the rds serial data stream. optionally it can be used as general purpose i/o controlled by dsp1. 23 rdsclk_ss/dsp1_gpio0 i spi chip select (input)/rds bit clock (output)/general purpose i/o (input/output). if spi is enabled, behaves as chip select line for spi bus. optionally it provides the 1187.5hz rds bit clock. optionally it can be used as general purpose i/o controlled by dsp1. 24 int i external interrupt line (input). when this line is asserted low, the dsp may be interrupted. acts as irqa line of dsp0 core. 25 cgnd1 ground pin dedicated to the digital circuitry. 26 cvdd1 supply pin dedicated to the digital circuitry. 27 scrccd i spdif input 1 (input). stereo spdif input to connect a digital audio source like a cd. 28 scrmd i spdif input 2 (input). stereo spdif input to connect a digital audio source like a md. 29 dsra<7> i/o dsp sram data lines<7> (input/output). when in sram mode this pin act as the emi data line 7. 30 dsra<6> i/o dsp sram data lines<6> (input/output). when in sram mode this pin act as the emi data line 6. n name type description pin description (continued)
5/40 tda7500a 31 dsra<5> i/o dsp sram data lines<5> (input/output). when in sram mode this pin act as the emi data line 5. 32 dsra<4> i/o dsp sram data lines<4> (input/output). when in sram mode this pin act as the emi data line 4. 33 dsra<3> i/o dsp sram data lines<3> (input/output)/dsp dram data line<3>(input/output). this pin act as the emi data line 3 in both sram mode and dram mode. 34 dsra<2> i/o dsp sram data lines<2> (input/output)/dsp dram data line<2>(input/output). this pin act as the emi data line 2 in both sram mode and dram mode. 35 dsra<1> i/o dsp sram data lines<1> (input/output)/dsp dram data line<1>(input/output). this pin act as the emi data line 1 in both sram mode and dram mode. 36 dsra<0> i/o dsp sram data lines<0> (input/output)/dsp dram data line<0>(input/output). this pin act as the emi data line 0 in both sram mode and dram mode. 37 sra<0> o dsp sram address line<0> (output)/dsp dram address line<0> (output). this pin acts as the emi address line 0 in both sram mode and dram mode 38 sra<1> o dsp sram address line<1> (output)/dsp dram address line<1> (output). this pin acts as the emi address line 1 in both sram mode and dram mode 39 sra<2> o dsp sram address line<2> (output)/dsp dram address line<2> (output). this pin acts as the emi address line 2 in both sram mode and dram mode 40 sra<3> o dsp sram address line<3> (output)/dsp dram address line<3> (output). this pin acts as the emi address line 3 in both sram mode and dram mode 41 sra<4> o dsp sram address line<4> (output)/dsp dram address line<4> (output). this pin acts as the emi address line 4 in both sram mode and dram mode 42 sra<5> o dsp sram address line<5> (output)/dsp dram address line<5> (output). this pin acts as the emi address line 5 in both sram mode and dram mode 43 sra<6> o dsp sram address line<6> (output)/dsp dram address line<6> (output). this pin acts as the emi address line 6 in both sram mode and dram mode 44 sra<7> o dsp sram address line<7> (output)/dsp dram address line<7> (output). this pin acts as the emi address line 7 in both sram mode and dram mode 45 sra<8> o dsp sram address line<8> (output)/dsp dram address line<8> (output). this pin acts as the emi address line 8 in both sram mode and dram mode n name type description pin description (continued)
tda7500a 6/40 46 sra<9> o dsp sram address line<9> (output)/dsp dram address line<9> (output). this pin acts as the emi address line 9 in both sram mode and dram mode 47 sra<10> o dsp sram address line<10> (output)/dsp dram address line<10> (output). this pin acts as the emi address line 10 in both sram mode and dram mode 48 sra<11> o dsp sram address line<11> (output)/dsp dram address line<11> (output). this pin acts as the emi address line 11 in both sram mode and dram mode 49 sra<12> o dsp sram address line<12> (output)/dsp dram address line<12> (output). this pin acts as the emi address line 12 in both sram mode and dram mode 50 cgnd2 ground pin dedicated to the digital circuitry. 51 cvdd2 supply pin dedicated to the digital circuitry. 52 sra<13> o dsp sram address line<13> (output)/dsp dram address line<13> (output). this pin act as the emi address line 13 in both sram mode and dram mode. 53 sra<14> o dsp sram address line<14> (output)/dsp dram address line<14> (output). this pin act as the emi address line 14 in both sram mode and dram mode. 54 sra<15> o dsp sram address line<15> (output)/dsp dram address line<15> (output). this pin act as the emi address line 15 in both sram mode and dram mode. 55 sra<16>/dsp0_gpio8 o dsp sram address line<16> (output)/dsp dram address line<16> (output)/general purpose i/o (input/output). this pin acts as the emi address line 16 in both sram mode and dram mode. optionally it can be used as general purpose i/o controlled by dsp0. after reset the state of this pin is read by the boot sw to select the boot mode (refer to hw/sw maual). 56 dwr o dsp sram write enable (output)/dram write enable (output). this pin serves as the write enable for the emi in both dram and sram mode (active low). to be connected to r/w of the ram. 57 drd o dsp sram read enable(output)/dram read enable (output). this pin serves as the read enable for the emi in both dram and sram mode (active low). to be connected to r/w of the ram. 58 casale o dsp dram column address strobe (output). when in dram mode this pin acts as the column address strobe. 59 sdo<2>/sra<17>/dsp1_gpio<8> o sai outputs (output)/emi sram address line<17> (output)/ general purpose i/o (input/output). one stereo channel sai data output in sai mode. emi address line 17 in sram mode. optionally it can be used as a general purpose i/o. n name type description pin description (continued)
7/40 tda7500a 60 sdo<2>/sra<18>/dsp1_gpio<7> o sai outputs (output)/emi sram address line<18> (output)/ general purpose i/o (input/output). one stereo channel sai data output in sai mode. emi address line 18 in sram mode. optionally it can be used as a general purpose i/o. 61 sdo<0>/sra<19> o sai output (output)/emi sram address line<19> (output). one stereo channel sai data output in sai mode. emi address line 19 in sram mode. 62 sdi<2>/sra<20>/dsp1_gpio<6> i sai input (input)/emi sram address line<20> (output)/ general purpose i/o (input/output). one stereo channel sai data input in sai mode. emi address line 20 in sram mode. optionally it can be used as a general purpose i/o. 63 sdi<1>/sra<21>/ras/dsp1_gpio<5> i sai input (input)/emi sram address line<21> (output)/dram row address strobe (output)/general purpose i/o (input/ output). one stereo channel sai data input in sai mode. emi address line 21 in sram mode. when in dram mode this pin acts as the row address strobe. optionally it can be used as a general purpose i/o. 64 sdi<0>/srccdc i sai input (input)/spdif input 3 (input). one stereo channel sai data input in sai mode. stereo spdif input intended to connect a digital audio source like a cd changer in spdif mode. 65 sckt i/o sai transmitter bit clock (input/output). sai transmitter bit clock. master or slave. 66 lrckt i/o sai transmitter left-right clock (input/output). sai transmitter left-right clock. can be master or slave mode. 67 sckr i sai receiver bit clock (input). sai receiver bit clock. slave only. 68 lrckr i sai receiver left-right clock (input/output). sai receiver left- right clock. slave only. 69 dbout1/dsp1_gpio10 i/o debug port serial output (input/output)/ general purpose i/o (input/output). the serial data output for the debug port. optionally it can be used as a general purpose i/o. 70 dbin1/os10/dsp1_gpio11 i/o debug port serial input/chip status 0 (input/output)/ general purpose i/o (input/output). the serial data input for the debug port is provided when an input. when an output, together with os1 provides information about the chip status. optionally it can be used as a general purpose i/o. 71 dbck1/os11/dsp1_gpio9 i/o debug port bit clock/chip status 1 (input/output)/general purpose i/o (input/output). the serial clock for the debug port is provided when an input. when an output, together with os0 provides information about the chip status. optionally it can be used as a general purpose i/o. 72 dbrqn1 i debug port request input (input). means of entering the debug mode of operation. 73 dbout0/dsp0_gpio10 i/o debug port serial output (input/output)/ general purpose i/o (input/output). the serial data output for the debug port. optionally it can be used as a general purpose i/o. n name type description pin description (continued)
tda7500a 8/40 74 dbin0/os00/dsp0_gpio11 i/o debug port serial input/chip status 0 (input/output)/ general purpose i/o (input/output). the serial data input for the debug port is provided when an input. when an output, together with os1 provides information about the chip status. optionally it can be used as a general purpose i/o. 75 dbck0/os01/dsp0_gpio9 i/o debug port bit clock/chip status 1 (input/output)/general purpose i/o (input/output). the serial clock for the debug port is provided when an input. when an output, together with os0 provides information about the chip status. optionally it can be used as a general purpose i/o. 76 dbrqn0 i debug port request input (input). means of entering the debug mode of operation. 77 vdd2 supply pin dedicated to the digital circuitry. 78 gnd2 ground pin dedicated to the digital circuitry. 79 adc<0> i analog inputs (input). single ended analog signal inputs to the adc. 80 adc<1> i analog inputs (input). single ended analog signal inputs to the adc. 81 adc<2> i analog inputs (input). single ended analog signal inputs to the adc. 82 adc<3> i analog inputs (input). single ended analog signal inputs to the adc. 83 s2dref i to be connected to adcgnd 84 adcvddref i voltage reference (input). analog voltage reference input. signal is supplied by a354. (typical 3.3v). 85 adcref<2> i voltage reference (input). external decoupling of the analog references used for the sigma delta modulator. 86 adcref<1> i voltage reference (input). external decoupling of the analog references used for the sigma delta modulator. 87 adcref<0> i voltage reference (input). external decoupling of the analog references used for the sigma delta modulator. 88 adcvdd analog supply pin dedicated to the a/d converter. 89 adcgnd analog ground pin dedicated to the a/d converter. 90 dac<0> o analog outputs (output). analog signal outputs of the dac 91 dac<1> o analog outputs (output). analog signal outputs of the dac 92 dac<2> o analog outputs (output). analog signal outputs of the dac 93 dac<3> o analog outputs (output). analog signal outputs of the dac 94 dac<4> o analog outputs (output). analog signal outputs of the dac 95 dac<5> o analog outputs (output). analog signal outputs of the dac n name type description pin description (continued)
9/40 tda7500a i/o definition and status o: logic low output x: undefined input/output z: high impedance 1: logic input output 96 dacref<2> i voltage reference (input). external decoupling of the analog references of the codec and voltage biasing. 97 dacref<1> i voltage reference (input). it can be connected to pin 100. 98 dacref<0> i voltage reference (input). external decoupling of the analog references of the codec and voltage biasing. 99 dacgnd analog ground pin dedicated to the d/a converter. 100 dacvdd analog supply pin dedicated to the d/a converter. pin # function reset state after boot i/o comments spi i 2 c emi 1 gnd1 supply 2 vdd1 supply to be connected to vdd 3 testen x x x x input to be connected to gnd 4 testse x x x x input ext. pulldown 5 nreset x x x x input 5vt 6 mspi: sckm input mspi: sckm output i2c: scl bi-direct dsp0: gpio0 input dsp0: gpio0 output x x (1) (1) input 5vt output 4ma pp input 5vt/output 4ma od input 5vt output 4ma od (1) undefined input 7 mspi: misom input mspi: misom output i2c: sda bi-direct dsp0: gpio1 input dsp0: gpio1 output x 0 or 1 x x x x input 5vt output 4ma od input 5vt/output 4ma od input 5vt output 4ma pp 8 mspi: mosim input mspi: mosim output dsp0: gpio2 input dsp0: gpio2 output x x x x input 5vt output 4ma od input 5vt output 4ma od 9 mspi: ssm input dsp0: gpio3 input dsp0: gpio3 output x x xx input 5vt input 5vt output 4ma pp 10 dspi: sckd input dspi: sckd output dsp0: gpio4 input dsp0: gpio4 output x x x x input 5vt output 4ma pp input 5vt output 4ma pp n name type description pin description (continued)
tda7500a 10/40 11 dspi: misod input dspi: misod output dsp0: gpio5 input dsp0: gpio5 output x xxx input 5vt output 4ma od input 5vt output 4ma od 12 dspi: mosid input dspi: mosid output dsp0: gpio6 input dsp0: gpio6 output x x x x input 5vt output 4ma od input 5vt output 4ma od 13 dspi: ssd input dsp0 : gpio7 input dsp0 : gpio7 output x x x input 5vt input 5vt output 4ma pp 14 pll: clkin input x x x x input 15 pll: avdd supply 16 pll: xti input x x x x analog input max. 20 mhz 17 pll: xto output x x x x analog output 18 pll: agnd supply 19 rds: rdsint output dsp1: gpio4 input dsp1: gpio4 output xxxx output 4ma pp onput 5vt output 4ma pp 20 rds: rdsari output rds spi: sck input dsp1: gpio3 input dsp1: gpio3 output xxxx output 4ma pp input 5vt input 5vt output 4ma pp 21 rds: rdsqal output rds spi: so input dsp1: gpio2 input dsp1: gpio2 output xxxx output 4ma od output 4ma od input 5vt output 4ma od 22 rds: rdsdat output rds spi: si input dsp1: gpio1 input dsp1: gpio1 output xxxx output 4ma pp input 5vt input 5vt output 4ma pp 23 rds: rdsclk output rds spi: ss input dsp1: gpio0 input dsp1: gpio0 output xxxx output 4ma pp input 5vt input 5vt output 4ma pp 24 int input x x x x input 5vt ext. pullup 25 cgnd1 supply 26 cvdd1 supply 27 scrccd input x x x x input 5vt 28 scrcmd input x x x x input 5vt 29 emi sram: data<7> bi-direct 1 1 1 z input/output 2ma pp pin # function reset state after boot i/o comments spi i 2 c emi i/o definition and status (continued)
11/40 tda7500a 30 emi sram: data<6> bi-direct 1 1 1 z input/output 2ma pp 31 emi sram: data<5> bi-direct 1 1 1 z input/output 2ma pp 32 emi sram: data<4> bi-direct 1 1 1 z input/output 2ma pp 33 emi sram: data<3> bi-direct emi sram: data<3> bi-direct 1 1 1 z input/output 2ma pp 34 emi sram: data<2> bi-direct emi sram: data<2> bi-direct 1 1 1 z input/output 2ma pp 35 emi sram: data<1> bi-direct emi sram: data<1> bi-direct 1 1 1 z input/output 2ma pp 36 emi sram: data<0> bi-direct emi sram: data<0> bi-direct 1 1 1 z input/output 2ma pp 37 emi sram: add<0> output emi sram: add<0> output 1 1 1 0/1 output 2ma pp output 2ma pp 38 emi sram: add<1> output emi sram: add<1> output 1 1 1 0/1 output 2ma pp output 2ma pp 39 emi sram: add<2> output emi sram: add<2> output 1 1 1 0/1 output 2ma pp output 2ma pp 40 emi sram: add<3> output emi sram: add<3> output 1 1 1 0/1 output 2ma pp output 2ma pp 41 emi sram: add<4> output emi sram: add<4> output 1 1 1 0/1 output 2ma pp output 2ma pp 42 emi sram: add<5> output emi sram: add<5> output 1 1 1 0/1 output 2ma pp output 2ma pp 43 emi sram: add<6> output emi sram: add<6> output 1 1 1 0/1 output 2ma pp output 2ma pp 44 emi sram: add<7> output emi sram: add<7> output 1 1 1 0/1 output 2ma pp output 2ma pp 45 emi sram: add<8> output emi sram: add<8> output 1 1 1 0/1 output 2ma pp output 2ma pp 46 emi sram: add<9> output emi sram: add<9> output 1 1 1 0/1 output 2ma pp output 2ma pp 47 emi sram: add<10> output emi sram: add<10> output 1 1 1 0/1 output 2ma pp output 2ma pp 48 emi sram: add<11> output emi sram: add<11> output 1 1 1 0/1 output 2ma pp output 2ma pp 49 emi sram: add<12> output emi sram: add<12> output 1 1 1 0/1 output 2ma pp output 2ma pp 50 cgnd2 supply 51 cvdd2 supply pin # function reset state after boot i/o comments spi i 2 c emi i/o definition and status (continued)
tda7500a 12/40 52 emi sram: add<13> output emi sram: add<13> output 1 1 1 0/1 output 2ma pp output 2ma pp 53 emi sram: add<14> output emi sram: add<14> output 1 1 1 0/1 output 2ma pp output 2ma pp 54 emi sram: add<15> output emi sram: add<15> output 1 1 1 0/1 output 2ma pp output 2ma pp 55 emi sram: add<16> output emi sram: add<16> output dsp0:gpio8 input dsp0: gpio8 output xxxx output 2ma pp output 2ma pp input output 2ma pp 56 emi sram: wr output emi dram: wr output 1 1 1 1 output 2ma pp output 2ma pp 57 emi sram: rd output emi dram: rd output 1 1 1 1 output 2ma pp output 2ma pp 58 emi sram: ale output emi dram: cas output 1 1 1 0 output 2ma pp output 2ma pp 59 sai: sdo2 output emi sram: add<17>output dsp1: gpio8 input dsp1: gpio8 output xxxx output 2ma pp output 2ma pp input output 2ma pp 60 sai: sdo1 output emi sram: add<18>output dsp1: gpio7 input dsp1: gpio7 output xxxx output 2ma pp output 2ma pp input output 2ma pp 61 sai: sdo0 output emi sram: add<19> output 1 1 1 1 output 2ma pp output 2ma pp 62 sai:sdi2 input emi sram: add<20> output dsp1: gpio6 input dsp1: gpio6 output xxxx input output 2ma pp input output 2ma pp 63 sai:sdi2 input emi sram: add<21> output emi dram: ras output dsp1: gpio5 input dsp1: gpio5 output xxxx input output 2ma pp output 2ma pp input output 2ma pp 64 sai: sdi0 input spdif: cd input x x x x input input 65 sai: sckt input sai: sckt output x x x x input output 2ma pp 66 sai: lrckt input sai: lrckt output x x x x input output 2ma pp 67 sai: sckr input x x x x input 68 sai: lrckr input x x x x input pin # function reset state after boot i/o comments spi i 2 c emi i/o definition and status (continued)
13/40 tda7500a 69 dsp1 debug: dbout output dsp1: gpio10 input dsp1: gpio10 output x 1 1 1 output 4ma pp input 5vt output 4ma pp after boot in debug mode 70 dsp1 debug: dbin input dsp1 : os10 output dsp1: gpio11 input dsp1: gpio11 output x x x x input 5vt output 4ma pp input 5vt output 4ma pp after boot in debug mode 71 dsp1 debug: dbck input dsp1 : os11 output dsp1: gpio9 input dsp1: gpio9 output x x x x input 5vt output 4ma pp input 5vt output 4ma pp after boot in debug mode 72 dsp1 debug: dbrqn input x x x x input 5vt after boot in debug mode 73 dsp0 debug: dbout output dsp0: gpio10 input dsp0: gpio10 output x 1 1 1 output 4ma pp input 5vt output 4ma pp after boot in debug mode 74 dsp0 debug: dbin input dsp0 : os00 output dsp0: gpio11 input dsp0: gpio11 output x x x x input 5vt output 4ma pp input 5vt output 4ma pp after boot in debug mode 75 dsp0 debug: dbck input dsp0 : os01 output dsp0: gpio9 input dsp0: gpio9 output x x x x input 5vt output 4ma pp input 5vt output 4ma pp after boot in debug mode 76 dsp0 debug: dbrqn input x x x x input 5vt 77 gnd2 supply 78 vdd2 supply 79 adc<0>input x x x x analog input 80 adc<1>input x x x x analog input 81 adc<2>input x x x x analog input 82 adc<3>input x x x x analog input 83 adc: s2dref input substrate biasing connected to gnd 84 adc: adcvddref input voltage reference connect 47 m f electolytic and 100nf ceramic parallel to adcgnd 85 adc: ref<2> input voltage reference connect 100 m f electolytic and 100nf ceramic parallel to adcgnd pin # function reset state after boot i/o comments spi i 2 c emi i/o definition and status (continued)
tda7500a 14/40 output pp : push-pull/ od : open-drain 5vt input: ttl five volt tolerant input - schmitt-trigger for all inputs. 86 adc: ref<1> input voltage reference connect 47 m f electolytic and 100nf ceramic parallel to adcgnd 87 adc: ref<0> input voltage reference connect 47 m f electolytic and 100nf ceramic parallel to adcgnd 88 adcvdd adc power supply 89 adcgnd adc ground 90 dac<0> output x x x x analog output 91 dac<1> output x x x x analog output 92 dac<2> output x x x x analog output 93 dac<3> output x x x x analog output 94 dac<4> output x x x x analog output 95 dac<5> output x x x x analog output 96 dac: ref<2> input voltage reference connect 47 m f electolytic and 100nf ceramic parallel to dacgnd 97 dac: ref<1> input voltage reference connect 47 m f electolytic and 100nf ceramic parallel to dacgnd (it can be connected to pin100) 98 dac: ref<0> input voltage reference connect to dacgnd (it can be connected to pin99) 99 dacgnd dac ground 100 dacvdd dac power supply pin # function reset state after boot i/o comments spi i 2 c emi i/o definition and status (continued)
15/40 tda7500a pin connection (top view) recommended dc operating conditions power consumption note: 45mhz internal dsp clock, 4adc and 6dac enabled. pll characteristics note: 1. depending on vco output frequency. 2. f dsp = f vco /2 when pll is running symbol parameter test condition min. typ. max. unit v dd 3.3v digital power supply voltage 3.15 3.3 3.45 v v cc 3.3v analog power supply voltage 3.15 3.3 3.45 v symbol parameter test condition min. typ. max. unit i dd total maximum current power supply @ 3.3v and t j = 125c 450 490 ma symbol parameter test condition min. typ. max. unit lock time (note1) power supply @ 3.3v and t j = 125c 3ms f vco vco frequency (note 2) 70 140 mhz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 testen testse nreset sckm mosim misom ssm sckd mosid misod ssd avdd xti xto clkin agnd rdsint rdsari_sck rdsdat_si rdsqal_so rdsclk_ss int cgnd1 cvdd1 scrccd dsra<7> dsra<6> dsra<5> dsra<4> dsra<3> dsra<2> dsra<1> dsra<0> sra<1> sra<0> sra<2> sra<3> sra<4> sra<5> sra<6> sra<7> sra<8> sra<9> sra<10> sra<11> sra<12> scrcmd cgnd2 dbck0os01 dbin0os00 dbout0 dbrqn1 dbck1_os11 dbin1_os10 dbout1 lrckr sckr lrckt sckt sdi0 sdi1/ sra<21> /ras sdi2 / sra<20> sdo0 / sra<19> sdo1 / sra<18> sdo2 / sra<17> casale drd dwr sra<15> sra<14> sra<13> cvdd2 sra<16> dacref0 dacref1 dacref2 dacvdd dacgnd dac5 dac4 dac3 dac2 dac1 dac0 adcref0 adcref1 adcref2 s2dref adcvddref adc3 adc1 adc2 adc0 adcgnd adcvdd gnd2 vdd2 dbrqn0 dsp0 gpio0 dsp0 gpio2 dsp0 gpio1 dsp0 gpio3 dsp0 gpio4 dsp0 gpio6 dsp0 gpio5 dsp0 gpio7 dsp1 gpio4 dsp1 gpio3 dsp1 gpio1 dsp1 gpio2 dsp1 gpio0 dsp0 gpio9 dsp0 gpio11 dsp0 gpio10 dsp0 gpio8 dsp1 gpio5 dsp1 gpio6 dsp1 gpio7 dsp1 gpio8 dsp1 gpio9 dsp1 gpio11 dsp1 gpio10 srccdc codec test iic/spi master spi displa y pll oscillator rds spdif emi sai debu g dsp1 debu g dsp0 gnd1 vdd1 emi spdif od od od od od od: 5v tolerant open drain output
tda7500a 16/40 oscillator characteristics general interface electrical characteristics note: 1. the leakage currents are generally very small, <1na. the value given here, 1ma, ia amaximum that can occur after an elec trostatic stress on the pin. 2. human body model. low voltage cmos interface dc electrical characteristics note: 1. takes into account 200mv voltage drop in both supply lines. 2. x is the source/sink current under worst case conditions and is reflected in the name of the i/o cell according to the drive capability. low voltage ttl interface dc electrical characteristics note: 1. ttl specifications only apply to the supply voltage range vdd = 3.0v to 3.6v 2. takes into account 200mv voltage drop in both supply lines. 3. x is the source/sink current under worst case conditions and is reflected in the name of the i/o cell according to the drive capability. symbol parameter test condition min. typ. max. unit f osc max oscillator frequency (xti) power supply @ 3.3v and t j = 125c 20 mhz symbol parameter test condition min. typ. max. unit l il low level input current without pullup device v i = 0v (note 1) 1 m a l ih high level input current without pullup device v i = v dd (note 1) 1 m a i oz tri-state output leakage without pull up/down device v o = 0v or v dd (note 1) 1 m a i ozft 5v tolerant tri-state output leakage without pull up/down device v o = 0v or v dd (note 1) 1 m a v o = 5.5v 1 3 m a i latchup i/o latch-up current v < 0v, v > v dd 200 ma v esd electrostatic protection leakage , 1 m a (note 2) 2000 v symbol parameter test condition min. typ. max. unit v il low level input voltage 0.2*v dd v v ih high level input voltage 0.8*v dd v v hyst schmitt trigger hysteresis 0.8 v v ol low level output voltage i ol = xma (notes 1, 2) 0.4 v v oh high level output voltage 0.85*v dd v symbol parameter test condition min. typ. max. unit v il low level input voltage (note 1) 0.8 v v ih high level input voltage (note 1) 2 v v ilhyst low level threshold input falling (note 1) 0.9 1.35 v v ihhyst low level threshold input falling (note 1) 1.3 1.9 v v hyst schmitt trigger hysteresis (note 1) 0.4 0.7 v v ol low level output voltage i ol = xma (notes 1, 2 & 3) 0.4 v v oh high level output voltage 2.4 v
17/40 tda7500a dsp core fm stereo decoder adc electrical characteristcs (t amb = 25c, v cc = 3.3v, measurement bandwidth 10hz to 20khz, a-weighted filter.) note1: 0db reference at 0.75v rms input adc electrical characteristcs (t amb = 25c, v cc = 3.3v, measurement bandwidth 10hz to 53khz.) symbol parameter test condition min. typ. max. unit f dsp maximum dsp clock frequency power supply @ 3.3v and t j = 125c 48 mhz symbol parameter test condition min. typ. max. unit a_ch channel separation >50 db thd total harmonic distortion 0.02 % (s+n)/n signal plus noise to noise ratio 86 db symbol parameter test condition min. typ. max. unit input voltage dynamic range 0.75 0.8 vrms sampling rate audio mode 48 khz attenuation @ 20khz @ fs = 44.1khz -0.6 db dynamic range -60db analog input 84 88 db snr 1khz; -3db analog input 84 88 db (thd + n) -3db analog input (note 1) -85 -80 db input impedance @ fs = 44.1khz 40 55 75 k w crosstalk 1vrms input @ 1khz -85 db gain mismatch between four input @ 1khz -0.5 0.5 db symbol parameter test condition min. typ. max. unit input voltage dynamic range 0.75 0.8 vrms sampling rate am-mode 192 khz dynamic range -60db analog input 80 db snr 1khz; -3db analog input 80 db (thd +n) -3db analog input -80 db
tda7500a 18/40 adc electrical characteristcs (t amb = 25c, v cc = 3.3v, measurement bandwidth 10hz to 160khz.) dac performance (t amb = 25c, v cc = 3.3v, measurement bandwidth 10hz to 20khz, a-weighted filter 0db gain, output load 30k w ) symbol parameter test condition min. typ. max. unit input voltage dynamic range 0.75 0.8 vrms sampling rate fm-mode 390 khz dynamic range -60db analog input 60 db snr 1khz; -3db analog input 60 db symbol parameter test condition min. typ. max. unit output voltage dynamic range 0.87 0.9 0.93 vrms sampling rate 48 khz attenuation @ 20khz @ 20khz with f s = 44.1khz -0.3 -0.2 db dynamic range -60db analog input 90 93 db snr 1khz -3db analog output 90 93 db digital silence 0000hex digital input 93 db (thd + n)/s @ digital full scale -85 -83 db output impedance 25 50 w crosstalk 1vrms output @ 1khz -90 -86 db gain mismatch between six outputs @ 1khz -0.5 0.5 db
19/40 tda7500a sai interface figure 1. sai timings note t dsp = dsp master clock cycle time = 1/f dsp figure 2. sai protocol when rlrs=0; rrel=0; rckp=1; rdir=0 timing description value unit t sckr minimum clock cycle 4t dsp ns t dt sckr active edge to data out valid 10 ns t lrs lrck setup time 5 ns t lrh lrck hold time 5 ns t sdid sdi setup time 15 ns t sdih sdi hold time 15 ns t sckph minimum sck high time 0.35 t sckr ns t sckpl minimum sck low time 0.35 t sckr ns sdi0-3 lrckr sckr (rckp=0) t lrh t sdis t sdih t lrs t sckpl t sckph valid valid t dt t sckr left right lsb(n-1) msb(word n) msb-1 (n) msb-2 (n) lrckr (#68) sckr (#67) sdi0,1,2 (#62, #63, #64)
tda7500a 20/40 figure 3. sai protocol when rlrs=1; rrel=0; rckp=1; rdir=1. figure 4. sai protocol when rlrs=0; rrel=0; rckp=0; rdir=0. figure 5. sai protocol when rlrs=0; rrel=1; rckp=1; rdir=0.
21/40 tda7500a spi interfaces figure 6. spi clocking scheme. 10 words main micro spi symbol description min value unit master t sclk clock cycle 12t dsp ns t dtr sclk edge to mosi valid 40 ns t misosetup miso setup time 16 ns t misohold miso hold time 4 ns t sclkh sck high time 0.5t sclk ns t sclkl sck high low 0.5t sclk ns slave t sclk clock cycle 12t dsp ns t dtr sclk edge to mosi valid 40 ns t mosisetup mosi setup time 16 ns t mosihold mosi hold time 4 ns t sclkh sck high time 0.5t sclk ns t sclkl sck high low 0.5t sclk ns display spi (different timings) master t sclk clock cycle 6t dsp ns slave t sclk clock cycle 6t dsp ns sclkd, sclkm (#6, #10) (cpol=0, cpha=0) misom, mosim (#7, #8) misod, mosid (#11, #12) ssm, ssd (#9, #13) (cpol=0, cpha=1) (cpol=1, cpha=0) (cpol=1, cpha=1) internal strobe for data capture msb 6 5 4 3 2 1 lsb sclkd, sclkm (#6, #10) sclkd, sclkm (#6, #10) sclkd, sclkm (#6, #10)
tda7500a 22/40 debug port interface figure 7. debug port serial clock timing. figure 8. debug port acknowledge timing. no. characteristics dclk = 40mhz unit min. max. 1 dbck rise time -- 3 ns 2 dbck fall time -- 3 ns 3 dbck low 40 -- ns 4 dbck high 40 -- ns 5 dbck cycle time 200 -- ns 6 dbrqn asserted to dbout (ack) asserted 5 tdsp -- ns 7 dbck high to dbout valid -- 42 ns 8 dbck high to dbout invalid 3 -- ns 9 dbin valid to dbck low (set-up) 15 -- ns 10 dbck low to dbin invalid (hold) 3 -- ns dbout (ack) asserted to first dbck high 2 tc -- ns dbout (ack) assertion width 4.5 tdsp - 3 5 tdsp + 7 ns 11 last dbck low of read register to first dbck high of next command 7 tdsp + 10 -- ns 12 last dbck low to dbout invalid (hold) 3 -- ns dbsel setup to dbck tdsp ns
23/40 tda7500a figure 9. debug port data i/o to status timing. figure 10. debug port read timing. figure 11. debug port dbck next command after read register timing.
tda7500a 24/40 external memory interface (emi) dram mode note: 1. n is the number of successive accesses. n = 2, 3, 4, or 6. dram refresh timing note: 1. happens when a refresh cycle is followed by an access cycle. characteristics timing mode 40mhz unit min. max. page mode cycle time slow fast 10075 ---- ns ns ras or rd assertion to data valid slow fast -- -- 159 109 ns ns cas assertion to data valid slow fast -- -- 65 40 ns ns column address valid to data valid slow fast -- -- 80 55 ns ns cas assertion to data active 0 -- ns ras assertion pulse width (note 1) (page mode access only) slow fast 264 189 -- -- ns ns ras assertion pulse width (single access only) slow fast 164 114 -- -- ns ns ras or cas negation to ras assertion slow fast 120 70 -- -- ns ns cas assertion pulse width slow fast 65 40 -- -- ns ns last cas assertion to ras negation (page mode access only) slow fast 60 35 -- -- ns ns characteristics timing mode 40mhz unit min. max. ras negation to ras assertion slow fast 143 93 -- -- ns ns cas negation to cas assertion slow fast 118 68 -- -- ns ns refresh cycle time slow fast 325 225 -- -- ns ns ras assertion pulse width slowf ast 166 116 -- -- ns ns ras negation to ras assertion for refresh cycle (note 1) slow fast 120 70 -- -- ns ns cas assertion to ras assertion on refresh cycle 18 -- ns ras assertion to cas negation on refresh cycle slow fast 160 110 -- -- ns ns ras negation to cas assertion on a refresh cycle slow fast 114 64 -- -- ns ns cas negation to data not valid 0 -- ns
25/40 tda7500a external memory interface (emi) sram mode figure 12. external memory interface sram read cycle. figure 13. external memory interface sram write cycle. characteristics 40mhz unit min. max. address valid and cs assertion pulse width 89 -- ns address valid to rd or wr assertion 23 -- ns rd or wr assertion pulse width 45 -- ns rd or wr negation to rd or wr assertion 39 -- ns rd or wr negation to address not valid 5 -- ns address valid to input data valid -- 72 ns rd assertion to input data valid -- 35 ns rd negation to data not valid (data hold time) 0 -- ns address valid to wr negation 73 -- ns data setup time to wr negation 32 -- ns data hold time from wr negation 5 -- ns wr assertion to data valid -- 18 ns wr negation to data high-z (note 1) -- 23 ns wr assertion to data active 5 -- ns add. [7:0] data add. [13:8] sra_d [7:0] sra_d [13:8] ale drd add. [7:0] data add. [13:8] sra [7:0] sra [13:8] ale dwr
tda7500a 26/40 figure 14. dram read cycle. figure 15. dram write cycle. dra [8:0] row address 1 column address 1 column address 2 row address 2 ras cas drd nibble 1 nibble 2 drd [3:0] row address 1 column address 1 column address 2 row address 2 dwr cas dra [8:0] ras nibble 1 nibble 2 drd[3:0]
27/40 tda7500a sample rate converter f sin /f sout = 1 (44.1khz) rds timing the rds block adhere to the timings defined by the rds standard en50067. more information are also available in the dedicated a ppllication note. symbol parameter test condition min. typ. max. unit thd+n total harmonic distortion + noise 20hz to 20khz, full scale, 16 bit inp. -98 db 20hz to 20khz, full scale, 20 bit inp. -101 db 1 khz full scale, 16 bit inp. -98 db 10 khz full scale, 16 bit inp. -98 db 1 khz full scale, 20 bit inp. -109 db 10 khz full scale, 20 bit inp -102 db dr dynamic range 1 khz -60 db - 16 bit inp.,a-weighted 98 db 1 khz -60 db - 20 bit inp.,a-weighted 120 db ipd interchannel phase deviation 0 degree f c cutoff frequency @ -3 db 20 hz r p pass band ripple from 0 to 20khz -0.05 +0.05 db r s stopband attenuation @24.1khz -105 db t g group delay fsout = 44.1 khz 612 m s f ratio f sin / f sout 0.7 1.05 symbol parameter test condition min. typ. max. unit f crystal crystal frequency first mode - 8.55 - mhz second mode - 8.664 - mhz t bclk rds spi bit clock (t dsp is the period of the dsp core) 3t dsp --ns t dis spi disable time between 2 transfers 3t dsp --ns
tda7500a 28/40 i 2 c timing figure 16. definition of timing for the i 2 c bus. spdif timing symbol parameter test condition standard mode i 2 c bus fast mode i 2 c bus unit min. max. min. max. f scl scll clock frequency 0 100 0 400 khz t buf bus free between a stop and start condition 4.7 C 1.3 C m s t hd:sta hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 C 0.6 C m s t low low period of the scl clock 4.7 C 1.3 C m s t high high period of the scl clock 4.0 C 0.6 C m s t su:sta set-up time for a repeated start condition 4.7 C 0.6 C m s t hd:dat data hold time 0 C 0 0.9 m s t r rise time of both sda and scl signals cb in pf C 1000 20+ 0.1c b 300 ns t f fall time of both sda and scl signals cb in pf C 300 20+ 0.1c b 300 ns t su;sto set-up time for stop condition 4 C 0.6 C m s t su:dat data set-up time 250 -- -- 100 ns c b capacitive load for each bus line C 400 C 400 pf symbol parameter test condition min. typ. max. unit spvl ac input level 0.2 0.5 3.3 vpp spir input impedance @ 1 khz C6Ck w sphys hysteresis of input C 40 C mv
29/40 tda7500a functional description the tda7500a ic broken up into two distinct blocks. one block contains the two dsp cores and their associ- ated peripherals. the other contains the adc, dac and the rds filter, demodulator and decoder. 24-bit dsp core the two dsp cores are used to process the audio and fm/am data, coming from the adc, either any kind of digital data coming via spdif or sai. after the digital signal processing these data are sent to the dac for an- alog conversion. functions such as volume, tone, balance, and fader control, as well as spatial enhancement and general purpose signal processing may be performed by the dsp0. when fm/am mode is selected, dsp1 is fully devoted to am/fm processing. nevertheless it can be used for any kind of different application, when a different input source is selected. some capabilities of the dsps are listed below: n single cycle multiply and accumulate with convergent rounding and condition code generation n 2 x 56-bit accumulators n double precision multiply n scaling and saturation arithmetic n 48-bit or 2 x 24-bit parallel moves n 64 interrupt vector locations n fast or long interrupts possible n programmable interrupt priorities and masking n 8 each of address registers, address offset registers and address modulo registers n linear, reverse carry, multiple buffer modulo, multiple wrap-around modulo address arithmetic n post-increment or decrement by 1 or by offset, index by offset, predecrement address n repeat instruction and zero overhead do loops n hardware stack capable of nesting combinations of 7 do loops or 15 interrupts/subroutines n bit manipulation instructions possible on all registers and memory locations, also jump on bit test n 4 pin serial debug interface n debug ccess to all internal registers, buses and memory locations n 5 word deep program address history fifo n hardware and software breakpoints for both program and data memory accesses n debug single stepping, instruction injection and disassembly of program memory dsp peripherals there are a number of peripherals that are tightly coupled to the two dsp cores. same of the peripherals are connected to dsp 0 others are connected to dsp1. n 5.5k x 24-bit program ram for dsp0 n 1k x 24-bit x-data ram for dsp0 n 1k x 24-bit y-data ram for dsp0 n 2k x 24-bit program ram for dsp1 n 1k x 24-bit x-data ram for dsp1 n 1k x 24-bit y-data ram for dsp1 n serial audio interface (sai) n spdif receiver with sampling rate conversion
tda7500a 30/40 n i2c and spi interface n xchg interface for dsp to dsp communication n external memory interface (dram/sram) for time-delay and traffic information n double debug port data and program memory both dsp0 and dsp1 have data and program memories attached to them. each of the memories are described below and it is implied that there are two of each type, one set connected to dsp0 and the other to dsp1. the only exception is the case of the p-ram where dsp1 has a 2048 x 24-bit pram and dsp0 has a 5.5k x 24- bit pram. 1024 x 24-bit x-ram (xram) this is a 1024 x 24-bit single port sram used for storing coefficients. the 16-bit xram address, xabx(15:0) is generated by the address generation unit of the dsp core. the 24-bit xram data, xdbx(23:0), may be writ- ten to and read from the data alu of the dsp core. the xdbx bus is also connected to the internal bus switch so that it can be routed to and from all peripheral blocks. 1024 x 24 bit y-ram (yram) this is a 512 x 24-bit single port sram used for storing coefficients. the 16-bit address, yabx(15:0) is gener- ated by the address generation unit of the dsp core. the 24-bit data, ydbx(23:0), is written to and read from the data alu of the dsp core. the ydbx bus is also connected to the internal bus switch so that it can be routed to and from other blocks. 2048 x 24-bit program ram (pram 5.5k x 24-bit for dsp0) this is a 2048 x 24-bit single port sram used for storing and executing program code. the 16-bit pram ad- dress, pabx(15:0) is generated by the program address generator of the dsp core for instruction fetching, and by the agu in the case of the move program memory (movem) instruction. the 24-bit pram data (pro- gram code), pdbx(23:0), can only be written to using the movem instruction. during instruction fetching the pdbx bus is routed to the program decode controller of the dsp core for instruction decoding. 512 x 24-bit bootstrap rom (prom 256 x 24 bit for dsp1) this is a 512 x 24-bit factory programmed boot rom used for storing the program sequence and for initializing the dsp. essentially this consists of reading the data via i2c, spi or emi interface and store it in pram, xram, yram, and/or external dram.
31/40 tda7500a figure 17. dsp1 and dsp0 memory spaces serial audio interface (sai) the sai is used to deliver digital audio to the dsps from an external source. once processed by the dsps, it can be returned through this interface either sent to the dac for d/a conversion. the features of the sai are listed below. n 3 synchronized stereo data transmission lines n 3 synchronized stereo data reception lines n master and slave operating mode: clock lines can be both master and slave. n receive and transmit data registers have two locations to hold left and right data. xchg interface (dsp to dsp exchange interface) the exchange interface peripheral provides bidirectional communication between dsp0 and dsp1. both 24 bit word data and four bit flag data can be exchanged. a fifo is utilized for received data. it minimizes the number of times an exchange interrupt service routine would have to be called if multi-word blocks of data were to be received. the transmit fifo is in effect the receive fifo of the other dsp and is written directly by the trans- mitting dsp. the features of the xchg are listed below. n 10 word xchg receive fifo on both dsps n four flags for each xchg for dsp to dsp signaling n condition flags can optionally trigger interrupts on both dsps dram/sram interface (emi) the external dram/sram interface is viewed as a memory mapped peripheral. data transfers are performed by moving data into/from data registers and the control is exercised by polling status flags in the control/status register or by servicing interrupts. an external memory write is executed by writing data into the emi data write register. an external memory read operation is executed by either writing to the offset register or reading the emi data read register, depending on the configuration. dsp1 $ffff $0000 x-space p-space $ffff not accessible not accessible y-space not accessible $ffff boot-space not accessible $07ff $0800 $00ff $ffc0 $0100 $ffbf dsp0 $ffff $0000 x-space p-space $ffff not accessible not accessible y-space not accessible $ffff boot-space not accessible $0200 $ffc0 $15ff $1600 $ffbf $01ff x-peripherals boot-rom p-ram $0400 $03ff x-peripherals x-ram y-ram boot-rom p-ram $0400 $03ff x-ram y-ram
tda7500a 32/40 the features of the emi are listed below. n data bus width fixed at 4 bits for dram and 8 bits for sram n data word length 16 or 24 bits for dram n data word length 8 or 16 or 24 bits for sram n dram address lines means 2 26 = 256mb addressable dram n refresh rate for dram can be chosen among eight divider factor n sram relative addressing mode; 2 22 = 4mb addressable sram n four sram timing choices n two read offset registers debug interface a dedicated debug port is available for each dsp cores. the debug logic is contained in the core design of the dsp. the features of the debug port are listed below: n breakpoint logic n trace logic n single stepping n instruction injection n program disassembly serial peripheral interface the dsp core requires a serial interface to receive commands and data over the lan. during an spi transfer, data is transmitted and received simultaneously. a serial clock line synchronizes shifting and sampling of the information on the two serial data lines. a slave select line allows individual selection of a slave spi device. when an spi transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simulta- neously shifted in a second data pin.the central element in the spi system is the shift register and the read data buffer. the system is single buffered in the transfer direction and double buffered in the receive direction. i 2 c interface the inter integrated circuit bus is a single bidirectional two-wire bus used for efficient inter ic control. all i 2 c bus compatible devices incorporate an on-chip interface which allows them communicate directly with each oth- er via the i 2 c bus. every component hooked up to the i2c bus has its own unique address whether it is a cpu, memory or some other complex function chip. each of these chips can act as a receiver and /or transmitter on its functionality. general purpose input/output the dsp requires a set of external general purpose input/output lines, and a reset line. these signals are used by external devices to signal events to the dsp. the gpio lines are implemented as dsp 's peripherals. the gpio lines are grouped in port a which is connected to dsp 0, and port b, which is connected to dsp1. rds the rds block is an hardware cell able to deliver the rds frames through a dedicated serial interface. rds quality signalis also available. this block needs to be initialised at reset by the dsp, after that it works in back- ground and does not need any further dsp support. rds is made of 57khz filter, demodulator and decoder.
33/40 tda7500a asynchronous sample rate converter the asrc, embedded in the tda7500a, offers a fully digital stereo asynchronous sample rate conversion of digital audio sources to the tda7500a's internal sample frequency. this solves the problem of mixing audio sources with different sample rates and doesn't need the "classical" approach of synchronizing the pll. as the usual internal sample rate of tda7500a is around 48.51 khz, the asrc works with the common input signals only in upsampling mode. there is no need to explicitly program the input and output sample rates, as the asrc solves this problem with an automatic digital ratio locked loop. the asrc is intended for applications up to 20 bit input word width. digital audio sources can be applied in general serial audio interface format (3 wires) as well as in aes/ebu, iec and eiaj cp-340 format (1 wire). an interface to the dsp core offers the possibility of interrupt controlled sample delivery. furthermore, a programma- ble control/status register inside the asrc allows a great variety of adjustments and status informations. figure 18. shows, how the asrc interfaces the other blocks. pll clock oscillator the pll clock oscillator can accept an external clock at xti or it can be configured to run an internal oscillator when a crystal is connected across pins xti & xto. there is an input divide block idf (1 -> 32) at the xti clock input and a multiply block mf (9 -> 128) in the pll loop. hence the pll can multiply the external input clock by a ratio mf/idf to generate the internal clock. this allows the internal clock to be within 1 mhz of any desired frequency even when xti is much greater than 1 mhz. it is recommended that the input clock is not divided down to less than 1 mhz as this reduces the phase detector's update rate. the clocks to the dsp can be selected to be either the vco output divided by 2 to 16, or be driven by the xti pin directly. the crystal oscillator and the pll will be gated off when entering the power-down mode (by setting a reg- ister on dsp0). figure 18. system overview di g ital audio sources e. g .: dat dab cd md broadcast 48 khz 48 khz 44.1 khz 44.1 khz 32 khz 3 lrckr_slv sckr_slv sdi0 sai receiver channel 0 1 s/pdif receiver aes/ebu iec 958 eiaj cp-340 left [19:0] ri g ht [19:0] fsin left [19:0] ri g ht [19:0] fsin asrc master clock source fsout * 256 dsp asynchr. sample rate converter
tda7500a 34/40 codec the codec is composed of four ad mono converters, three da stereo converters. the adc can operate both in audio mode and in fm/am mode. when in audio mode, it converts the audio bandwidth from 20 to 20khz. the a to d is a third order sigma-delta converter, the converter resolutions is 20 bit with 88 db of dynamic range and 85db of total harmonic distortion. when in fm mode, the converted bandwidth is up to 192khz. the d to a is a third order sigma-delta converter with a low noise reconstructing analog filter, the converter resolution is 20 bit with 93 db of dynamic range and 85db of total harmonic distortion. all the reference voltages are generated inside the chip. some capabilities of the codec are listed below: n 20-bit resolution n digital anti-alias filtering embedded n adjustable system sampling rates n 93db d/a dynamic range (not-weighted)88db a/d dynamic range (not-weighted) n 85db d/a (thd+n/s)85db a/d (thd+n/s) n internal differential analog architecture n +3.3v power supply software features a great flexibility is guaranteed by the two programmable dsp cores. a list of the main software functions which can be implemented in the tda7500a is enclosed hereafter. a block diagram of the audio process- ing flow is shown in fig. 19 below. figure 19. software block diagram of audio & sound processing am/fm baseband signal processing n fm weak signal processing n integrated 19 khz mpx filter and deemphasis n flexible noise cancellation n flexible multipath detector generic audio signal processsing n loudness n bass, treble, fader control n volume control dly dly dly hp peq t b ld drc rm anr sm + dly hp peq t b ld drc anr sm dly lp audio noise reduction d y namic ran g e compression loudness bass treble parametric e q ualiser soft mute routin g matrix delay stereo input rf cf lf rr lr sw
35/40 tda7500a n distortion limiting n premium equalization n soft mute tape signal processsing n dolby b noise reduction n automatic music search cd signal proceessing n dynamic range compression audiophile n parametric equalization n crossover n channel delays n center channel imaging output n audio noise reduction other n voice compression/decompression for tim storage n echo and noise cancelling for mobile phone connection application scheme the tda7500a can operate as a standalone device either it can interface the tda7501 which contains the analog input multiplexer, analog volume control and the line-driver. the fm_mpx and fm_level sig- nals coming from the tuner and other signals supplied by analog sources are adapted by the tda7501 and fed to the tda7500a. a block diagram of the system is shown in fig. 20 below. the tda7500a converts all the analog signals into digital domain and performs am/fm processing and audio/sound processing. thanks to this, it is possible to process any audio source as well analog as digital in parallel, to record fm mono for traffic information, telephone response, navigation and rds. finally the digital signals are d/a converted and sent to the tda7501 for the final level adjustment and for the analog volume control.
tda7500a 36/40 figure 20. lock diagram of car amplifier audio sub-system. clock scheme when tda7500a is used in ad/fm mode the following scheme is choosen in order to avoid harmonics inside the fm band. parts of the system are directly clocked by the crystal oscillator, whereas other parts are driven by the pll oscillator. thanks to this it is possible to process any audio source as well analog as digital in parallel to record fm mono for traffic informations, telephone resp. navigation and rds. figure 21 shows the clock scheme. regarding on the country and its fm bandwidth different crystals should be selected. figure 21. clock scheme tda7501 analog input tda7500a front end tda7421 audio power display micro digital out main micro dram/ sram eeprom/ flash digital in spdif i 2 c/spi fig20tda7500a a/d d/a int./ext. 8.55 mhz fext: 44.1 khz, 48khz osc fcomp: 1.425 mhz (8.55/6) 1.411 mhz (44.1*2*16) 1.536 mhz (48*2*16) fvco: 173.85 mhz (fcomp*122) 158.05 mhz (fcomp*112) 172.03 mhz (fcomp*112) a/d fm-mpx/ stereo audio a/d mono level / tel. / navi. a/d fm-rds / noise det. rds -demod. audio dsp d/a coverters fconverter: 12.42 mhz (fvco/14) 11.29 mhz (fvco/14) 12.29 mhz (fvco/14) fdsp: 43.46 mhz (fvco/4) 39.51 mhz (fvco/4) 43.01 mhz (fvco/4) pll stereo dsp faudio: 48.51 khz 44.1 khz 48 khz frds: 8.55 mhz (fxtal) xtal fm japan west europe east 76..90 87.5..108 65..74 [mhz] 86.92 86.92 8.89 mhz 90.38 90.38 2nd hamonics 3rd hamonics 135.57 135.57 130.38 130.38
37/40 tda7500a application diagram the application diagram shown on the next page must be considered as one of the examples of a (limited) ap- plication of the chip. for the real application set-up the application notes are necessary. figure 22. application diagram. m p gnd1 spi1 gpio3 nreset gnd1 dacref0 dacgnd vdd1 testen 5 1 99 98 testse 4 2 3 c3 10 m f sckw misom 6 7 mosim ssm 8 9 spi2 scko miooo 10 11 mosio sso 12 13 clkin 14 to ext memory to ext memory sai interface (**) debug interface gpio8 casale drd 58 57 drr sra15 56 54 sra14 sra13 53 52 sdi0 sdi1/sra21/ras 64 63 sdi2/sra20 sdo0/sra19 62 61 lcrckr sckr 68 67 lrckt sckt 66 65 dbck1-os11 dbin1-os10 71 70 dbout1 69 dbckoos01 dbinoos00 75 74 dbout0 dbron1 73 72 dbcron0 adc0 adc1 adc2 adc3 adcvdoref adcref2 ain3 ain2 ain1 ain0 76 79 80 81 82 84 out0 90 85 sdo1/sra18 sdo2/sra17 60 59 rds interfaces rdsint rdsari-sck 19 20 rdsqual-so rdsdat-si 21 22 rdssclk-ss int 23 24 sra16 cvdd2 cvdd2 d00au1195 nreset cvdd2 cgnd2 55 51 gnd2 adcgnd vref gnd2 vdd2 vdd2 78 77 adcgnd adcgnd adcvd00 adcvd00 89 88 avdd 15 agnd agnd xti avdd agnd c1 22pf c2 22pf 18 16 xto xtal r1 1m 17 cgnd1 25 cvdd1 scrccd scrcm0 cgnd1 cvdd1 spdif1 r11 100 r12 100 spdif2 26 27 28 dsra7 29 dsra6 30 dsra5 31 dsra4 32 dsra3 33 dsra2 34 dsra1 35 dsra0 36 sra0 37 sra1 38 sra2 39 sra3 40 sra4 41 sra5 42 sra6 43 sra7 44 sra8 45 sra9 46 sra10 47 sra11 48 sra12 49 cgnd2 50 (**) when not used all pins connected to cgnd2 r2 10k r4 10k r3 10k r5 10k r9 10k r7 10k r8 10k r10 10k r6 10k 4 x 1 m f c16 100nf c15 47 m f c14 100nf c13 100 m f adcref1 adcref0 dacref2 dacvcc dacref1 s2dref 86 87 83 96 97 adcgnd dacgnd c10 100nf c9 47 m f c12 100nf c5 100nf c11 47 m f c4 47 m f c7 100nf c6 47 m f c8 4.7 m f out1 dac0 dac1 91 out2 92 out3 dac2 dac3 93 out4 94 out5 dac4 dac5 95 100 test 0 * * = connected to cgnd2 o = connected to cvdd2 pin9 gpio3 pin55 gpio8 0 * 0 * 1 o 1 o 1 o 1 o 0 * i 2 c emi spi tda7500 a
tda7500a 38/40 package marking
39/40 tda7500a outline and mechanical data a a2 a1 ccc seating plane c c c 25 26 50 51 75 76 100 d3 d1 d e 1 b s1 s h tqfp100m gage plane 0.25mm .010 inch pin 1 identification k l l1 e3 e1 e dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.003 0.008 d 16.00 0.630 d1 14.00 0.551 d3 12.00 0.472 e 0.50 0.020 e 16.00 0.630 e1 14.00 0.551 e3 12.00 0.472 h 9.85 0.388 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 s 8.80 0.346 s1 8.80 0.346 k 0? (min.), 3.5? (typ.), 7?(max.) ccc 0.080 0.003 tqfp100 (14x14x1.40mm) with slug down (10x10mm)
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